MPC8540 datasheet(744/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-118

Freescale Semiconductor

Three-Speed Ethernet Controllers

write zeros to the hash in order to avoid a hash match, and ones to station address in order to avoid

individual address match, or the user can turn on promiscuous mode. (See Section 14.5.3.4.1,

“Receive Control Register (RCTRL).”)

In the group type of address recognition, the Ethernet controller determines whether the group

address is a broadcast address. If it is a broadcast, and broadcast addresses are enabled, the frame

is accepted. If the group address is not a broadcast address, the user can perform address

recognition on multiple group addresses using the GADDRn hash table. In promiscuous mode, the

Ethernet controller receives all of the incoming frames regardless of their address.

14.6.2.6.2 Hash Table Algorithm

The hash table process used in the individual and group hash filtering operates as follows. The

Ethernet controller maps any 48-bit destination address into one of 256 bins, represented by the

256 bits in GADDR0–7 or IADDR0–7. The eight high-order bits of a cyclic redundancy check

(CRC) checksum are used to index into the hash table. The high-order three bits of this 8-bit field

are used to select one of the eight registers in either the individual or group hash table. The

low-order five bits select a bit within the 32-bit register. A value of 0 in the high-order three bits

selects IADDR0/GADDR0.

The same process is used if the Ethernet controller receives a frame. If the CRC checksum selects

a bit that is set in the group/individual hash table, the frame is accepted. If 32 group addresses are

stored in the hash table and random group addresses are received, the hash table prevents roughly

224/256 (87.5%) of the group address frames from reaching memory. Software must further filter

those that reach memory to determine if they contain the correct addresses.

Better performance is achieved by using the group and individual hash tables in combination. For

instance, if 32 group and 32 physical addresses are stored in their respective hash tables, because

87.5% of all group addresses and 87.5% of all individual address are rejected, then 87.5% of all

frames are prevented from reaching memory.

The effectiveness of the hash table declines as the number of addresses increases. For instance, as

the number of addresses stored in the 256-bin hash table increases, the vast majority of the hash

table bits are set, preventing only a small fraction of frames from reaching memory.

14.6.2.6.3 CRC Computation Examples

There are many algorithms for calculating the CRC value of a number. Refer to the RFC 3309

standard, which can be found at http://www.faqs.org/rfcs/rfc3309.html, to compute the CRC value

for the purposes of TSEC. The RFC 3309 algorithm uses the following polynomial to calculate the

CRC value: x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x1+x0 or 0x04c11db7.

Given a destination MAC address of DA=01000CCCCCCC, the algorithm results in a CRC

remainder value of 0xA29F4BBC.

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