MPC8540 datasheet(741/1302 Pages) FREESCALE

741 / 1302 page

Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

14-115

or terminates with an error. The IEVENT[GTSC] interrupt occurs once the graceful transmit stop

operation is completed. After GTS is cleared, the TSEC resumes transmission with the next frame.

While the TSEC is in 10/100 Mbps mode it sends bytes least-significant nibble first and each

nibble is sent lsb first. While it is in 1-Gbps mode it sends bytes lsb first.

14.6.2.4 Gigabit Ethernet Frame Reception

The TSEC Ethernet receiver is designed to work with little core intervention and can perform

address recognition, CRC checking, short frame checking, and maximum frame-length checking.

The receiver can also force frame headers and buffer descriptors to be allocated into the L2 cache.

See Section 14.6.4, “Data Extraction to the L2 Cache,” for additional information.

After a hardware reset, the software driver clears the RSTAT register and sets

MACCFG1[RX_EN]. The Ethernet receiver is enabled and immediately starts processing receive

frames. If TSECn_RX_DV is asserted and TSECn_COL remains negated, the MAC strips a valid

preamble/SFD (start of frame delimiter) header and begins processing the frame. If a valid header

is not found, the frame is ignored.

If the receiver detects the first bytes of a frame, the TSEC controller begins to perform the frame

recognition function through destination address (DA) recognition (See Section 14.6.2.6, “Frame

Recognition,” for additional information.). Based on this match the frame can be accepted or

rejected. Once accepted, the TSEC processes the frame based on user-defined attributes.

The receiver can also filter frames based on physical (individual), group (multicast), and broadcast

addresses. Because Ethernet receive frame data is not written to memory until the internal frame

recognition algorithm is complete, system bus usage is not wasted on frames unwanted by this

station.

If a frame is accepted, the Ethernet controller fetches the receive buffer descriptor (RxBD) from

the queue. If RxBD is not being used by software (RxBD[E] is set), the TSEC starts transferring

the incoming frame. RxBD[F] is set for the first RxBD used for any particular receive frame.

If the buffer is filled, the TSEC controller clears RxBD[E] and, if RxBD[I] is set, generates an

interrupt. If the incoming frame is larger than the buffer, the Ethernet controller fetches the next

RxBD in the table. If it is empty, the controller continues receiving the rest of the frame. In

half-duplex mode, if a collision is detected during the frame, no RxBDs are used; thus, no collision

frames are presented to the user except late collisions, which indicate LAN problems.

The RxBD length is determined by the MRBL field in the maximum receive buffer length register

(MRBL). The smallest valid value is 64 bytes. During reception, the Ethernet controller checks for

frames that are too short or too long. After the frame ends (CRS is negated), the receive CRC field

is checked and written to the data buffer. The data length written to the last RxBD in the Ethernet

frame is the length of the entire frame, which enables the software to recognize a frame-too-long

condition.

MPC8540 Datasheet(PDF) 741 Page - Freescale Semiconductor, Inc