MPC8540 datasheet(737/1302 Pages) FREESCALE

737 / 1302 page

Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

14-111

Table 14-112 describes the signals shared by all interfaces.

14.6.2 Gigabit Ethernet Channel Operation

This section describes the operation of the TSEC. First, the software initialization sequence is

described. Next, the software (Ethernet driver) interface for transmitting and receiving frames is

reviewed. Address recognition and hash table algorithm features are also discussed. The section

concludes with interrupt handling, inter-packet gap time, and loop back descriptions.

14.6.2.1 Initialization Sequence

This section describes which registers are reset due to a hard or software reset and what registers

the user must initialize prior to enabling the TSEC.

14.6.2.1.1 Hardware-Controlled Initialization

A hard reset occurs when the system powers up. All TSEC registers and control logic are reset to

their default states after a hard reset has occurred.

14.6.2.1.2 User Initialization

After the system has undergone a hard reset, software must initialize certain basic TSEC registers.

Other registers can also be initialized during this time, but they are optional and must be

determined based on the requirements of the system. The module memory map in Table 14-3 lists

all the TSEC registers. Table 14-113 describes the minimum steps for register initialization.

Table 14-112. Shared Signals

Signals

I/O

# of signals

Function

EC_MDIO

I/O

Management interface I/O

EC_MDC

Management interface

clock

EC_GTX_CLK125

Reference clock

Sum

Table 14-113. Steps of Minimum Register Initialization

Description

1. Set, then clear MACCFG1 [Soft_Reset]

2. Initialize MACCFG2

3. Initialize MAC station address

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