MPC8540 datasheet(733/1302 Pages) FREESCALE

733 / 1302 page

Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

14-107

Figure 14-113. TSEC-TBI Connection

A TBI interface has 27 signals (EC_GTX_CLK125 included) for connecting to an Ethernet PHY,

as defined by IEEE 802.3z GMII and TBI standards.

14.6.1.5 Reduced Ten-Bit Interface (RTBI)

This section describes the reduced ten-bit interface (RTBI) intended to be used between the PHYs

and the TSEC to implement a reduced signal count version of a SerDes interface for optical-fiber

devices in 1000BASE-SX/LX applications. Figure 14-114 shows the basic components of the

RTBI including the signals required to establish TSEC module connection with a PHY.

Transmit Data (TSECn_TXD[9:0])

GigaBit Transmit Clock (TSECn_GTX_CLK)

Receive Data (TSECn_RXD[9:0])

TBI Receive Clock 0 (TSECn_RX_CLK0)

TBI Receive Clock 1 (TSECn_RX_CLK1)

Management Data I/O1 (EC_MDIO)

Management Data Clock1 (EC_MDC)

TSEC

Gigabit

PHY

Medium

1 The management signals (EC_MDC and EC_MDIO) are common to all of the Ethernet controllers’

connections in the system, assuming that each PHY has a different management address.

Gigabit Reference Clock (EC_GTX_CLK125)

SIGNAL DETECT (SDET)

Ethernet

MPC8540 Datasheet(PDF) 733 Page - Freescale Semiconductor, Inc