MPC8540 datasheet(730/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-104

Freescale Semiconductor

Three-Speed Ethernet Controllers

14.6.1.1 Media-Independent Interface (MII)

This section describes the media-independent interface (MII) intended to be used between the

PHYs and the TSEC. Figure 14-110 shows the basic components of the MII including the signals

required to establish TSEC module connection with a PHY.

Figure 14-110. TSEC-MII Connection

An MII interface has 18 signals (including the EC_MDC and EC_MDIO signals), as defined by

the IEEE 802.3u standard, for connecting to an Ethernet PHY.

14.6.1.2 Gigabit Media-Independent Interface (GMII)

This section describes the gigabit media-independent interface (GMII) intended to be used

between the PHYs and the TSEC. Figure 14-111 shows the basic components of the GMII

including the signals required to establish the TSEC module connection with a PHY.

Transmit Error (TSECn_TX_ER)

Transmit Data (TSECn_TXD[3:0])

Transmit Enable (TSECn_TX_EN)

Transmit Clock (TSECn_TX_CLK)

Collision Detect (TSECn_COL)

Receive Data (TSECn_RXD[3:0])

Receive Error (TSECn_RX_ER)

Receive Clock (TSECn_RX_CLK)

Receive Data Valid (TSECn_RX_DV)

Carrier Sense Output (TSECn_CRS)

Management Data I/O1 (EC_MDIO)

Management Data Clock1 (EC_MDC)

TSEC

10/100

PHY

Medium

1 The management signals (EC_MDC and EC_MDIO) are common to all of the Ethernet controllers’

connections in the system, assuming that each PHY has a different management address.

Ethernet

MPC8540 Datasheet(PDF) 730 Page - Freescale Semiconductor, Inc