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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-102

Freescale Semiconductor

Three-Speed Ethernet Controllers

Table 14-108 describes the fields of the JD register.

14.5.4.11 TBI Control Register (TBICON)

Figure 14-109 shows the TBICON register.

Table 14-108. JD Field Description

Bits

Name

Description

Jitter Enable Jitter enable. This bit is cleared by default.

0 Normal transmit operation

1 Enable the TBI to transmit the jitter test patterns defined in annex 36A of the IEEE 802.3

specification.

1–3

Jitter Select

Selects the jitter pattern to be transmitted in diagnostics mode. Encoding of this field is shown in the

following table. Default is 0

4–5

—

Reserved

6–15

Custom Jitter

Pattern

Used in conjunction with jitter (pattern) select and jitter (diagnostic) enable; set this field to the

desired custom pattern which is continuously transmitted. Its default is 0.

1011

Soft_Reset

Disable

Rx Dis

Disable

Tx Dis

Sense

Clock

Select

MII

Mode

Reset

0000_0000_0000_0000

Offset

TBIPA offset + 0x11

Figure 14-109. TBI Control Register Definition

Jitter Pattern Select

bit[1]

bit[2]

bit[3]

User defined uses custom jitter pattern, bits 6–15

High frequency (±D21.5)

1010101010101010101010101010101010101010…

Mixed frequency (±K28.5)

1111101011000001010011111010110000010100…

Low frequency

1111100000111110000011111000001111100000…

Complex pattern (10’h17c,10’h0c9,10’h0e5,10’h2a3, 10’h17c,...)

Square Wave (-K28.7)

0011111000001111100000111110000011111000…

Reserved

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