MPC8540 datasheet(724/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-98

Freescale Semiconductor

Three-Speed Ethernet Controllers

14.5.4.6 AN Expansion Register (ANEX)

Figure 14-104 shows the ANEX register.

Table 14-104 describes the fields of the ANEX register.

14.5.4.7 AN Next Page Transmit Register (ANNPT)

Figure 14-105 shows the ANNPT register.

000

Able

Page

Rx’d

Reset

0000_0000_0000_0110

Offset

TBIPA offset + 0x06

Figure 14-104. AN Expansion Register Definition

Table 14-104. ANEX Field Descriptions

Bits

Name

Description

0–12

—

Reserved, must be cleared.

Able

Next page able. This bit is read-only and returns 1 on read. While read as set, indicates local device

supports next page function

Page

Rx’d

Page received. This bit is read-only. The bit clears on a read to the register.

0 Normal operation

1 A new page was received and stored in the applicable AN link partner ability or AN next page register.

This bit latches high in order for software to detect while polling.

—

Reserved, must be cleared.

Ack

Msg Page

Ack2

Toggle

Message/Unformatted Code Field

Reset

0000_0000_0000_0000

Offset

TBIPA offset + 0x07

Figure 14-105. AN Next Page Transmit Register Definition

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