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MPC8540 Datasheet(PDF) 722 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 722 Page - Freescale Semiconductor, Inc |
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722 / 1302 page ![]() MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 14-96 Freescale Semiconductor Three-Speed Ethernet Controllers Table 14-102 describes the resolution of pause priority. 14.5.4.5 AN Link Partner Base Page Ability Register (ANLPBPA) Figure 14-103 shows the ANLPBPA register. Table 14-102. PAUSE Priority Resolution Local Device Link Partner Local Resolution Link Partner Resolution PAUSE ASM_DIR PAUSE ASM_DIR 0 0 x x Disable PAUSE transmit Disable PAUSE receive Disable PAUSE transmit Disable PAUSE receive 0 1 0 x Disable PAUSE transmit Disable PAUSE receive Disable PAUSE transmit Disable PAUSE receive 0 1 1 0 Disable PAUSE transmit Disable PAUSE receive Disable PAUSE transmit Disable PAUSE receive 0 1 1 1 Enable PAUSE transmit Disable PAUSE receive Disable PAUSE transmit Enable PAUSE receive 1 0 0 x Disable PAUSE transmit Disable PAUSE receive Disable PAUSE transmit Disable PAUSE receive 1 0 1 x Enable PAUSE transmit Enable PAUSE receive Enable PAUSE transmit Enable PAUSE receive 1 1 0 0 Disable PAUSE transmit Disable PAUSE receive Disable PAUSE transmit Disable PAUSE receive 1 1 0 1 Disable PAUSE transmit Enable PAUSE receive Enable PAUSE transmit Disable PAUSE receive 1 1 1 x Enable PAUSE transmit Enable PAUSE receive Enable PAUSE transmit Enable PAUSE receive 01 2 3 4 6 7 8 9 10 11 15 RNext Page Ack Remote Fault 00 0 Pause Half Duplex Full Duplex 00 0 0 0 W Reset 0000_0000_0000_0000 Offset TBIPA offset + 0x05 Figure 14-103. AN Link Partner Base Page Ability Register Definition |
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