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MPC8540 Datasheet(PDF) 723 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 723 Page - Freescale Semiconductor, Inc |
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723 / 1302 page  Memory Map/Register Definition MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 Freescale Semiconductor 14-97 Table 14-103 describes the fields of the ANLPBPA register. Table 14-103. ANLPBPA Field Descriptions Bits Name Description 0Next Page Next page. This bit is read-only. The link partner sets or clears this bit. 0 Link partner has no subsequent next pages or is not capable of receiving next pages 1 Link partner either requesting next page transmission or indicating the capability to receive next pages 1 Ack Acknowledge. Ignore on read. This bit is read-only 2–3 Remote Fault The link partner’s remote fault condition is encoded in bits 2 and 3 of the base page. Values are shown in the remote fault encoding field table below. This bit is read-only. 4–6 — Reserved, must be cleared. 7–8 Pause Encoding of the link partner’s PAUSE capability is shown in the PAUSE encoding table below. For priority resolution information consult the IEEE 802.3 specification. This bit is read-only 9Half Duplex Half-duplex capability. This bit is read-only. 0 Link partner is not capable of half-duplex mode 1 Link partner is capable of half-duplex mode 10 Full Duplex Full-duplex capability. This bit is read-only. 0 Link partner is not capable of full-duplex mode 1 Link partner is capable of full-duplex mode 11–15 — Reserved, must be cleared. RF1 bit[3] RF2 bit[2] Description 0 0 No error, link OK 0 1 Offline 1 0 Link_Failure 1 1 Auto-Negotiation_Error PAUSE bit[8] ASM_DIR bit[7] Capability 0 0 No PAUSE 0 1 Asymmetric PAUSE toward link partner 10 Symmetric PAUSE 1 1 Both symmetric PAUSE and Asymmetric PAUSE toward local device |
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