MPC8540 datasheet(720/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-94

Freescale Semiconductor

Three-Speed Ethernet Controllers

14.5.4.4 AN Advertisement Register (ANA)

Figure 14-102 shows the ANA register.

Table 14-101 describes the fields of the ANA register.

Ability

Auto-negotiation ability. While read as set, this bit indicates that the PHY has the ability to perform

auto-negotiation. While read as cleared, this bit indicates the PHY lacks the ability to perform

auto-negotiation. Returns 1 on read. This bit is read-only.

Link

Status

Link status. This bit is read-only and is cleared by default.

0 A valid link is not established. Latches low allowing for software polling to detect a failure condition.

1 A valid link is established.

—

Reserved, must be cleared.

Extend

Ability

Extended capability. This bit indicates that the PHY contains the extended set of registers (those beyond

control and status). Returns 1 on read. This bit is read-only.

1011

R Next

Page

Ack

Remote

Fault

Pause

Half

Duplex

Full

Duplex

Reset

0000_0000_0000_0000

Offset

TBIPA offset + 0x04

Figure 14-102. AN Advertisement Register Definition

Table 14-101. ANA Field Descriptions

Bits

Name

Description

0Next

Page

Next page configuration. The local device sets this bit to either request next page transmission or

advertise next page exchange capability.

0 The local device wishes not to engage in next page exchange.

1 The local device has no next pages but wishes to allow reception of next pages. If the local

device has no next pages and the link partner wishes to send next pages, the local device shall

send null message codes and have the message page set to 0b000_0000_0001, as defined in

annex 28C of the IEEE 802.3 specification.

Ack

Acknowledge. Write 0, ignore on read.This bit is read-only. (Reserved)

Table 14-100. SR Descriptions (continued)

Bits

Name

Description

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