MPC8540 datasheet(716/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-90

Freescale Semiconductor

Three-Speed Ethernet Controllers

14.5.3.9.2 Attribute Extract Length and Extract Index Register (ATTRELI)

The ATTRELI registers are written by the user to specify the extract index and extract length.

Figure 14-99 shows the ATTRELI register.

Table 14-97 describes the fields of the ATTRELI register.

—

Reserved

20–21

BDLWT Buffer descriptor L2 cache write type. Specifies the write transaction type to perform for the buffer

descriptor for a receive frame. Writes to cache are always performed with snoop.

00 No allocation performed. This setting overrides the RBDSEN bit setting.

01 Reserved

10 Allocate L2 cache line

11 Allocate and lock L2 cache line

22–23

—

Reserved

RDSEN Rx data snoop enable. This bit is superseded by the ELCWT settings.

0 Disables snooping of all receive frames data to memory unless ELCWT specifies L2 allocation

1 Enables snooping of all receive frames data to memory

RBDSEN RxBD snoop enable. This bit is superseded by the BDLWT settings.

0 Disables snooping of all receive BD memory accesses unless BDLWT specifies L2 allocation

1 Enables snooping of all receive BD memory accesses

26–31

—

Reserved

15 16 17 18

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_4BFC; TSEC2:0x2_5BFC

Figure 14-99. ATTRELI Register Definition

Table 14-97. ATTRELI Field Descriptions

Bits

Name

Description

0–1

—

Reserved

2–15

Extracted length. Specifies the number of bytes to extract from the receive frame. The DMA controller

uses this field to perform extraction. If set to zero, no extraction is performed.

16–17

—

Reserved

18–31

Extracted index. Points to the first byte within the receive frame from which to begin extracting data.

Table 14-96. ATTR Field Descriptions (continued)

Bits

Name

Description

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