MPC8540 datasheet(714/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-88

Freescale Semiconductor

Three-Speed Ethernet Controllers

14.5.3.8.1 Individual Address Registers 0–7 (IADDRn)

The IADDRn registers, shown in Figure 14-96, are written by the user. These registers represent

256 entries of the individual (unicast) address hash table used in the address recognition process.

When the DA field of a receive frame is processed through a 32-bit CRC generator, the 8

high-order bits (0–7) of the CRC remainder are mapped to one of the 256 entries. The user can

enable a hash entry by setting the appropriate bit. A hash table hit occurs if the DA CRC result

points to an enabled hash entry.

Table 14-94 describes the field of the IADDRn registers.

14.5.3.8.2 Group Address Registers 0–7 (GADDRn)

The GADDRn registers are written by the user. Together these registers represent 256 entries of

the group (multicast) address hash table used in the address recognition process. While the DA

field of a receive frame is processed through a 32-bit CRC generator, the 8 bits of the CRC

remainder is mapped to one of the 256 entries. The user can enable a hash entry by setting the

appropriate bit. A hash table hit occurs if the DA CRC result points to an enabled hash entry.

Figure 14-97 shows the GADDRn registers.

IADDRn

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_4800, 0x2_4804, 0x2_4808, 0x2_480C, 0x2_4810, 0x2_4814, 0x2_4818, 0x2_481C

TSEC2:0x2_5800, 0x2_5804, 0x2_5808, 0x2_580C, 0x2_5810, 0x2_5814, 0x2_5818, 0x2_581C

Figure 14-96. IADDRn Register Definition

Table 14-94. IADDRn Field Description

Bits

Name

Description

0–31 IADDRn Represents the 32-bit value associated with the corresponding register. IADDR0 contains the

high-order 32 bits of the 256-entry hash table and IADDR7 represents the low-order 32 bits. For

instance, the MSB of IADDR0 correlates to entry 0 and the LSB of IADDR7 correlates to entry 255.

GADDRn

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_4880, 0x2_4884, 0x2_4888, 0x2_488C, 0x2_4890, 0x2_4894, 0x2_4898, 0x2_489C

TSEC2:0x2_5880, 0x2_5884, 0x2_5888, 0x2_588C, 0x2_5890, 0x2_5894, 0x2_5898, 0x2_589C

Figure 14-97. GADDRn Register Definition

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