MPC8540 datasheet(718/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-92

Freescale Semiconductor

Three-Speed Ethernet Controllers

14.5.4.2 Control Register (CR)

Figure 14-100 shows the CR register.

Table 14-99 describes the fields of the CR register.

PHY Reset

Speed_0

AN Enable

Reset AN

Full Duplex

Speed_1

0 0000 0

Reset

0001_0001_0100_0000

Offset

TBIPA offset + 0x00

Figure 14-100. Control Register Definition

Table 14-99. CR Field Descriptions

Bits

Name

Description

PHY Reset

PHY reset. This bit is cleared by default. This bit is self-clearing.

0 Normal operation.

1 The control and status registers are returned to their default value. This in turn may change the

internal state of the TBI and its link partner.

1—

Reserved

Speed_0

Speed selection. This bit defaults to a cleared state and must always be cleared, which

corresponds to 1-Gbps speed.

AN Enable

Auto-negotiation enable. This bit is set by default.

0 The values programmed in bits 2, 7 and 9 determine the operating condition of the link.

1 Auto-negotiation process enabled

4–5

—

Reserved

Reset AN

Reset auto-negotiation. This bit is cleared by default and is self-clearing.

0 Normal operation

1 The auto-negotiation process restarts. This action is only available if auto-negotiation is

enabled.

Full Duplex

Duplex mode. This bit is set by default.

0 Half-duplex operation

1 Full-duplex operation

—

Reserved, must be cleared.

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