MPC8540 datasheet(717/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

14-91

14.5.4 Ten-Bit Interface (TBI)

This section describes the ten-bit interface (TBI) and the TBI MII set of registers.

14.5.4.1 TBI MII Set Register Descriptions

This section describes the TBI MII registers. All TBI registers are 16 bits wide and are accessed

at the offset of the TBI physical address. The TBI physical address of the TSEC is stored in TBIPA.

Writing to the TBI registers is similar to writing to an external PHY, by using the MII management

interface. By using TBIPA in place of the PHY address, in the MIIMADD[PHY Address] field,

and setting MIIMADD[Register Address] to the address offset that corresponds to the desired

MIIMCON[PHY control]) to the TBI block. Refer to the TBI physical address register in

Section 14.5.3.1, “TSEC General Control and Status Registers,” and the TBI MII register set in

Table 14-98.

Note that jitter diagnostics and TBI control are not IEEE 802.3 required registers and are only used

for test and control of the TSEC TBI block. The TBI’s TBI control register (TBI) is for configuring

the TSEC ten-bit interface block. However, because this TBI block has an MII management

interface (just like any other PHY), it has an IEEE 802.3 register called the control register (CR).

Table 14-98. TBI MII Register Set

Offset

Name

Access

Size

Section/Page

TEN-BIT INTERFACE (TBI) REGISTERS

14.5.4/14-91

0x00

Control (CR)

R/W1

1 R = means read only, WO = write only, R/W = read and write, LH = latches high, LL = latches low,

SC = self-clearing.

16 bits

14.5.4.2/14-92

0x01

Status (SR)

R, LH, LL

16 bits

14.5.4.3/14-93

0x02–0x03

Reserved

2 bytes

—

0x04

AN advertisement (ANA)

RW, R

16 bits

14.5.4.3/14-93

0x05

AN link partner base page ability (ANLPBPA)

16 bits

14.5.4.5/14-96

0x06

AN expansion (ANEX)

R, LH

16 bits

14.5.4.6/14-98

0x07

AN next page transmit (ANNPT)

R/W, R

16 bits

14.5.4.7/14-98

0x08

AN link partner ability next page (ANLPANP)

16 bits

14.5.4.8/14-99

0x0F

Extended status (EXST)

16 bits

14.5.4.9/14-100

0x10

Jitter diagnostics (JD)

R/W

16 bits

14.5.4.10/14-101

0x11

TBI control (TBICON)

R/W

16 bits

14.5.4.11/14-102

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