MPC8540 datasheet(715/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

14-89

Table 14-95 describes GADDRn.

14.5.3.9 Attribute Registers

This section describes the two TSEC frame attribute registers.

14.5.3.9.1 Attribute Register (ATTR)

The attribute register, shown in Figure 14-98, defines attributes and transaction types used to

access buffer descriptors, to write receive data, and to read transmit data. Snoop enable attributes

may be set for reading buffer descriptors and for reading transmit data. Buffer descriptors may be

written with attributes that cause allocation into the L2 cache with or without line locking.

Similarly, sections of a receive frame header may have attributes attached that cause allocation and

locking in the L2 cache. This process of specifying a region of each frame to stash into the L2

cache is referred to as extraction, which is specified in conjunction with ATTRELI.

ATTR[ELCWT] only has meaning if ATTRELI[EL] is non-zero.

Table 14-96 describes the fields of the ATTR register.

Table 14-95. GADDRn Field Description

Bits

Name

Description

0–31

GADDRn Represents the 32-bit value associated with the corresponding register. GADDR0 contains the

high-order 32 bits of the 256-entry group hash table and GADDR7 represents the low-order 32 bits.

For instance, the MSB of GADDR0 correlates to entry 0 and the LSB of GADDR7 correlates to

entry 255.

1920

2122 23

R 0 00 000000000000 0 0

ELCWT

BDLWT

RDSEN RBDSEN

00 0 0 0 0

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_4BF8; TSEC2:0x2_5BF8

Figure 14-98. ATTR Register Definition

Table 14-96. ATTR Field Descriptions

Bits

Name

Description

0–16

—

Reserved

17–18 ELCWT Extracted L2 cache write type. Specifies the write transaction type to perform for the extracted data.

This occurs only if ATTRELI[EL] is non-zero. For maximum performance, it is recommended that if

ELCWT is set to allocate, BDLWT must also be set to allocate. Writes to cache are always performed

with snoop. This setting overrides the RDSEN bit setting.

00 No allocation performed

01 Reserved, no extraction occurs

10 Allocate L2 cache line

11 Allocate and lock L2 cache line

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