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MPC8540 Datasheet(PDF) 719 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 719 Page - Freescale Semiconductor, Inc |
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719 / 1302 page ![]() Memory Map/Register Definition MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 Freescale Semiconductor 14-93 14.5.4.3 Status Register (SR) Figure 14-101 shows the SR register. Table 14-100 describes the fields of the SR register. 9 Speed_1 Speed selection. Defaults to a set state and must always be set, which corresponds to 1 Gbps 10–15 — Reserved 06 7 8 9 10 11 12 13 14 15 R 0 0 00 00 0 Extend Status 0 No Pre AN Done Remote Fault AN Ability Link Status 0 Extend Ability W Reset 0000_0001_0100_1001 Offset TBIPA offset + 0x01 Figure 14-101. Status Register Definition Table 14-100. SR Descriptions Bits Name Description 0–6 — Reserved, must be cleared. 7Extend Status Indicates that PHY status information is also contained in the Extended Status Register. Returns 1 on read. This bit is read-only. 8 — Reserved, must be cleared. 9No Pre MF preamble suppression enable. This bit indicates whether or not the PHY is capable of handling MII management frames without the 32-bit preamble field. Returns 1, indicating support for suppressed preamble MII management frames. This bit is read-only. 10 AN Done Auto-negotiation complete. This bit is read-only and is cleared by default. 0 Either the auto-negotiation process is underway or the auto-negotiation function is disabled. 1 The auto-negotiation process has completed. 11 Remote Fault Remote fault. This bit is read-only and is cleared by default. Each read of SR clears this bit. 0 Normal operation 1 A remote fault condition was detected. Latches high for software to detect the condition. Table 14-99. CR Field Descriptions (continued) Bits Name Description Maximum Operating Speed Bit 2 Bit 9 Reserved 0 0 Reserved 1 0 1 Gbps 0 1 Reserved 1 1 |
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