MPC8540 datasheet(729/1302 Pages) FREESCALE

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Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

14-103

Table 14-109 describes the fields of the TBICON register.

14.6 Functional Description

This section describes many of the functions of the TSEC controller.

14.6.1 Connecting to Physical Interfaces

This section describes how to connect the TSEC to various interfaces: MII, GMII, RGMII, RTBI

and TBI. To avoid confusion, all of the buses follow the bus conventions used in the IEEE 802.3

specification, because each PHY follows the same convention. (For instance, in the bus

TSECn_TXD[7:0], bit 7 is the MSB and bit 0 is the LSB).

Table 14-109. TBICON Field Descriptions

Bits

Name

Description

Soft_Reset

Soft reset. This bit is cleared by default.

0 Normal operation

1 Resets the functional modules in theTBI

—

Reserved. (Ignore on read)

Disable Rx Dis Disable receive disparity. This bit is cleared by default.

0 Normal operation

1 Disables the running disparity calculation and checking in the receive direction

Disable Tx Dis Disable transmit disparity. This bit is cleared by default.

0 Normal operation

1 Disables the running disparity calculation and checking in the transmit direction

4–6

—

Reserved

7AN

Sense

Auto-negotiation sense enable. This bit is cleared by default.

0 IEEE 802.3z Clause 37 behavior is desired, which results in the link not completing.

1 Allow the auto-negotiation function to sense either a Gigabit MAC in auto-negotiation

bypass mode or an older Gigabit MAC without auto-negotiation capability. If sensed,

auto-negotiation complete becomes true; however, the page received is low, indicating no

page was exchanged. Management can then act accordingly.

8–9

—

Reserved

Clock

Select

Clock select. This bit is cleared by default.

0 Allow the TBI to accept dual split-phase 62.5-MHz receive clocks.

1 Configure the TBI to accept a 125-MHz receive clock from the SerDes/PHY. The 125-MHz

clock must be physically connected to ‘PMA receive clock 0’.

MII

Mode

This bit describes the configuration mode of the TBI. The user reads a 1 while the TBI is

configured in GMII/MII mode (connected to a GMII/MII PHY) and a 0 while configured in TBI

mode (connected to a 1000BASE-X SerDes). Its value is the inverse of ECNTRL[TBIM].

0TBI mode

1 GMII mode

12–15

—

Reserved

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