MPC8540 datasheet(732/1302 Pages) FREESCALE

732 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-106

Freescale Semiconductor

Three-Speed Ethernet Controllers

Figure 14-112. TSEC-RGMII Connection

14.6.1.4 Ten-Bit Interface (TBI)

This section describes the ten-bit interface (TBI) intended to be used between the PHYs and the

TSEC to implement a standard SerDes interface for optical-fiber devices in 1000BASE-SX/LX

applications. Figure 14-113 shows the basic components of the TBI including the signals required

to establish TSEC module connection with a PHY. RBC0 and RBC1 are differential 62.5-MHz

receive clocks.

Transmit Data (TSECn_TXD[3:0]/TSECn_TXD[7:4])

Transmit Control (TX_EN/f(TX_EN,TX_ER))

Gigabit Transmit Clock (TSECn_GTX_CLK)

Receive Data (TSECn_RXD[3:0]/TSECn_RXD[7:4])

Receive Control (RX_DV/f(RX_DV,RX_ER))

Receive Clock (TSECn_RX_CLK)

Management Data I/O1 (EC_MDIO)

Management Data Clock1 (EC_MDC)

TSEC

Medium

1 The management signals (EC_MDC and EC_MDIO) are common to all of the gigabit Ethernet controllers

module connections in the system, assuming that each PHY has a different management address.

Gigabit Reference Clock (EC_GTX_CLK125)

Gigabit

PHY

Ethernet

MPC8540 Datasheet(PDF) 732 Page - Freescale Semiconductor, Inc