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MPC8540 Datasheet(PDF) 734 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 734 Page - Freescale Semiconductor, Inc

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
14-108
Freescale Semiconductor
Three-Speed Ethernet Controllers
Figure 14-114. TSEC-RTBI Connection
A RTBI interface has 15 signals (EC_GTX_CLK125 included), as defined by the RGMII
specification Version 1.2a 9/22/00, and is intended to be an alternative to the IEEE 802.3u MII,
the IEEE 802.3z GMII and the TBI standard for connecting to an Ethernet PHY.
Table 14-110 describes the signal multiplexing for GMII, MII and TBI interfaces.
Table 14-110. GMII, MII, and TBI Signal Multiplexing
TSEC Signals
Frequency [MHz] 125
Voltage[V] 3.3/2.5
GMII Interface
Frequency [MHz] 125
Voltage[V] 3.3
MII Interface
Frequency [MHz] 25
Voltage[V] 3.3
TBI Interface
Frequency [MHz] 62.5
Voltage[V] 3.3
Signals
(TSECn_)
I/O
No. of
Signals
Signals
(TSECn_)
I/O
No. of
Signal
s
Signals
(TSECn_)
I/O
No. of
Signal
s
Signals
(TSECn_)
I/O
No. of
Signal
s
GTX_CLK
O
1
GTX_CLK
O
1
GTX_CLK
O
1
TX_CLK
I
1
TX_CLK
I
1
TX_CLK
I
1
RX_CLK1
I
1
TxD[0]
O
1
TxD[0]
O
1
TxD[0]
O
1
TCG[0]
O
1
TxD[1]
O
1
TxD[1]
O
1
TxD[1]
O
1
TCG[1]
O
1
TxD[2]
O
1
TxD[2]
O
1
TxD[2]
O
1
TCG[2]
O
1
TxD[3]
O
1
TxD[3]
O
1
TxD[3]
O
1
TCG[3]
O
1
TxD[4]
O
1
TxD[4]
O
1
TCG[4]
O
1
TxD[5]
O
1
TxD[5]
O
1
TCG[5]
O
1
TxD[6]
O
1
TxD[6]
O
1
TCG[6]
O
1
TxD[7]
O
1
TxD[7]
O
1
TCG[7]
O
1
Transmit Data (TSECn_TXD[4:0]/TSECn_TXD[9:5])
GigaBit Transmit Clock (TSECn_GTX_CLK)
Receive Data (TSECn_RXD[4:0]/TSECn_RXD[9:5])
Receive Clock (TSECn_RX_CLK)
Management Data I/O1 (EC_MDIO)
Management Data Clock1 (EC_MDC)
TSEC
Gigabit
PHY
Medium
1 The management signals (EC_MDC and EC_MDIO) are common to all of the Ethernet controllers’
connections in the system, assuming that each PHY has a different management address.
Gigabit Reference Clock (EC_GTX_CLK125)
Ethernet



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