MPC8540 datasheet(738/1302 Pages) FREESCALE

738 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-112

Freescale Semiconductor

Three-Speed Ethernet Controllers

After the registers are initialized, the user must execute the following steps in the order described

below to bring the TSEC into a functional state (out of reset):

1. For the transmission of Ethernet frames, TxBDs must first be built in memory, linked

together as a ring, and pointed to by the TBASE register. A minimum of two buffer

descriptors per ring is required. Setting the ring to a size of one causes the same frame to

be transmitted twice.

2. Likewise, for the reception of Ethernet frames, the receive queue must be ready, with its

RxBD pointed to by the RBASE register. Both transmit and receive can be gracefully

stopped after transmission and reception begins.

3. Write to MACCFG1 and set the appropriate bits. These need to include Rx_EN and

Tx_EN. To enable flow control, Rx_Flow and Tx_Flow must also be set.

4. Clearing DMACTRL[GTS] triggers the transmission of frame data if the transmitter had

been previously stopped. DMACTRL[GRS] must be cleared if the receiver had been

previously stopped. See Section 14.5.3.1.7, “DMA Control Register (DMACTRL),” and

Section 14.6.3.1, “Transmit Data Buffer Descriptor (TxBD),” for more information.

14.6.2.2 Soft Reset and Reconfiguring Procedure

Before issuing a soft reset to and/or reconfiguring the MAC with new parameters, user must

properly shutdown the DMA and make sure it is in an idle state for the entire duration. User must

gracefully stop the DMA by setting both GRS and GTS bits in the DMACTRL register, then wait

for both GRSC and GTSC bits to be set in the IEVENT register before resetting the MAC or

changing parameters. Both GRS and GTS bits must be cleared before re-enabling the MAC to

resume the DMA.

During the MAC configuration, if a new set of Tx buffer descriptors are used, the user must load

the pointers into the TBASE register. Likewise if a new set of Rx buffer descriptors are used, the

RBASE register must be written with the new pointer.

4. Set up the PHY using the MII Mgmt Interface

5. Configure the TBI control to TBI or GMII

6. Clear IEVENT

7. Initialize IMASK

8. Initialize IADDRn

9. Initialize GADDRn

10. Initialize RCTRL

11. Initialize DMACTRL

Table 14-113. Steps of Minimum Register Initialization (continued)

Description

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