MPC8540 datasheet(739/1302 Pages) FREESCALE

739 / 1302 page

Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

14-113

Following is a procedure to gracefully reset and reconfigure the MAC:

1. Set GTS bit in DMACTRL register.

2. Poll GTSC bit in IEVENT register until detected as set.

3. Clear both Rx_EN and Tx_EN bits in MACCFG1.

4. Wait for a period of 9.6 Kbytes worth of data on the interface (~8ms worst case).

5. Set GRS bit in DMACTRL register.

6. Poll GRSC bit in IEVENT register until detected as set.

7. Set Soft_Reset bit in MACCFG1 register.

8. Clear Soft_Reset bit in MACCFG1 register.

9. Load TBASE with new TxBD pointer.

10. Load RBASE with new RxBD pointer.

11. Set up other MAC registers (MACCFG2, MAXFRM, and so on).

12. Set WWR and WOP bits in DMACTRL register.

13. Clear THLT bit in TSTAT register and QHLT bit in RSTAT register by writing 1 to these

bits.

14. Clear GRS/GTS bits in DMACTRL. (Do not change other bits.)

15. Enable Tx_EN/Rx_EN in MACCFG1 register.

14.6.2.3 Gigabit Ethernet Frame Transmission

The Ethernet transmitter requires little core intervention. After the software driver initializes the

system, the TSEC begins to poll the first transmit buffer descriptor (TxBD) in the TxBD ring every

512 transmit clocks. If TxBD[R] is set, TSEC begins moving transmit buffer from memory to its

Tx FIFO. The transmitter takes data from the Tx FIFO and transmits data to the MAC. The MAC

transmits the data through the GMII interface to the physical media. The transmitter, once

initialized, runs until the end-of-frame (EOF) condition is detected unless a collision within the

collision window occurs (half-duplex mode) or an abort condition is encountered.

If the user has a frame ready to transmit, a transmit-on-demand function may be emulated while

in polling mode by using the graceful-transmit-stop feature. First, clear the IMASK[GTSCEN] bit

to mask the graceful-transmit-stop complete interrupt. Next set, then immediately clear the

DMACTRL[GTS] bit. Clear the resulting IEVENT[GTSC] bit. Finally, the IMASK[GTSCEN] bit

may be set once again.

There is one internal buffer for out-of-sequence flow control frames. While the TSEC is between

frames, this buffer is polled. The buffer must contain the whole frame. Once the TSEC is in paused

mode, the out-of-sequence buffer descriptor cannot be used to send another flow control frame

because the MAC regards it as a regular TxBD.

MPC8540 Datasheet(PDF) 739 Page - Freescale Semiconductor, Inc