MPC8540 datasheet(740/1302 Pages) FREESCALE

740 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-114

Freescale Semiconductor

Three-Speed Ethernet Controllers

In half-duplex mode (MACCFG2[Full Duplex] is cleared) the MAC defers transmission if the line

is busy (CRS asserted). Before transmitting, the MAC waits for carrier sense to become inactive,

at which point it then determines if CRS remains negated for 60 clocks. If so, transmission begins

after an additional 36 bit times (96 bit times after CRS originally became negated). If CRS

continues to be asserted, the MAC follows a specified back-off procedure and tries to retransmit

the frame until the retry limit is reached. Data stored in the Tx FIFO is re-transmitted in case of a

collision. This improves bus usage and latency.

The transmitter also monitors for an abort condition and terminates the current frame if an abort

condition is encountered. In full-duplex mode the protocol is independent of network activity, and

only the transmit inter-frame gap must be enforced.

The transmit block also implements full-duplex flow control. If a flow control frame is received,

the MAC does not service the transmitter’s request to send data until the pause duration is over. If

the MAC is currently sending data when a pause frame is received, the MAC finishes sending the

current frame, then suspends subsequent frames (except a pause frame) until the pause duration is

over. The pause duration is defined by the received pause control frame and begins when the frame

was first received. In addition, the transmitter supports transmission of flow control frames via

TCTRL[TFC_PAUSE]. The transmit pause frame is generated internally based on the PAUSE

the pause timer has not expired.

The MAC automatically appends FCS (32-bit CRC) bytes to the frame if any of the following

values are set:

•

TxBD[PAD/CRC] is set in first TxBD

•

TxBD[TC] is set in first TxBD

•

MACCFG2[PAD/CRC] is set

•

MACCFG2[CRC EN] is set

Following the transmission of the FCS, the Ethernet controller writes the frame status bits into the

BD and clears TxBD[R]. If the end of the current buffer is reached and TxBD[L] is cleared (a

frame is comprised of multiple buffer descriptors), only TxBD[R] is cleared.

For both half- and full-duplex modes, an interrupt can be issued depending on TxBD[I]. The

Ethernet controller then proceeds to the next TxBD in the table. In this way, the core can be

interrupted after each frame, after each buffer, or after a specific buffer is sent. If

TxBD[PAD/CRC] is set, the Ethernet controller pads any frame shorter than 64 bytes.

To pause transmission or rearrange the transmit queue, set DMACTRL[GTS]. This can help in

transmitting expedited data ahead of previously linked buffers or for error situations. If GTS is set,

the TSEC transmitter performs a graceful transmit stop. The Ethernet controller stops immediately

if no transmission is in progress or continues transmission until the current frame either finishes

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