MPC8540 datasheet(756/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-130

Freescale Semiconductor

Three-Speed Ethernet Controllers

14.6.4 Data Extraction to the L2 Cache

Some applications require the ability to identify selected portions of data within a frame’s data

payload. This process is called extraction; although, the data is not truly removed. Rather than

literarily extracting a section of the data and copying it into a new memory location, the data is

placed in the L2 cache. This allows the processor to quickly access critical frame information as

soon as the processor is ready without having to first fetch the data from main memory. This

reduction in latency can result in a substantial improvement in packet processing throughput.

Extraction functionality is controlled and configured with ATTR and ATTRELI. See

Section 14.5.3.9.1, “Attribute Register (ATTR),” and Section 14.5.3.9.2, “Attribute Extract

Length and Extract Index Register (ATTRELI),” for specific register information.

Offset + 0

Broadcast. Written by TSEC. (Only valid if L is set.) Is set if the DA is broadcast

(FF-FF-FF-FF-FF-FF)

Offset + 0

Multicast. Written by TSEC. (Only valid if L is set.) Is set if the DA is multicast and not BC

Offset + 0

Rx frame length violation. Written by TSEC. (Only valid if L is set.) A frame length greater than

maximum frame length was recognized while MACCFG2[Huge Frame] was set. Note, if

MACCFG2[Huge Frame] is cleared, the frame is truncated to the value programmed in the

Maximum Frame Length register.

Offset + 0

Rx non-octet aligned frame. Written by TSEC. (Only valid if L is set.) A frame that contained a

number of bits not divisible by eight was received.

Offset + 0

Short frame. Written by TSEC. (only valid if L is set.) A frame length that was less than the

minimum length defined for this channel (MINFLR) was recognized, provided RCTRL[RSF] is

set.

Offset + 0

Rx CRC error. Written by TSEC. (Only valid if L is set.) This frame contains a CRC error and

is an integral number of octets in length.This bit is also set if a receive code group error is

detected.

Offset + 0

Overrun. Written by TSEC. (Only valid if L is set.) A receive FIFO overrun occurred during

frame reception. If this bit is set, the other status bits, M, LG, NO, SH, CR, and CL lose their

normal meaning and are zero.

Offset + 0

Truncation. Written by TSEC. (Only valid if L is set.) Is set if the receive frame is truncated.

This can happen if a frame length greater than maximum frame length was received and the

MACCFG2[Huge Frame] is cleared. If this bit is set, the frame must be discarded and the other

error bits must be ignored as they may be incorrect.

Offset + 2 0–15

Data

Length

Data length. Written by TSEC. Data length is the number of octets written by the TSEC into

this BD’s data buffer if L is cleared (the value is equal to MRBL), or the length of the frame

including CRC, if L is set.

Offset + 4 0–31

Rx Data

Buffer

Pointer

Receive buffer pointer. Written by user. The receive buffer pointer, which always points to the

first location of the associated data buffer, must be 64-byte aligned. The buffer must reside in

memory external to the TSEC.

Table 14-121. Receive Buffer Descriptor Field Descriptions (continued)

Offset

Bits

Name

Description

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