MPC8540 datasheet(755/1302 Pages) FREESCALE

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Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

14-129

MC, LG, NO, SH, CR, OV, and TR bits in the first word of the buffer descriptor are only modified

by the TSEC if the L bit is set. The first word of the RxBD contains control and status bits. Its

format is detailed in Figure 14-119 below.

Table 14-121 describes the fields of the RxBD.

0123456

789

Offset + 0

RO1

BCMCLG

CROV

Offset + 2

Data Length

Offset + 4

RX Data Buffer Pointer

Offset + 6

Figure 14-119. Receive Buffer Descriptor

Table 14-121. Receive Buffer Descriptor Field Descriptions

Offset

Bits

Name

Description

Offset + 0

Empty. Written by TSEC (when cleared) and by user (when set).

0 The data buffer associated with this BD is filled with received data, or data reception is

aborted due to an error condition. The status and length fields have been updated as

required.

1 The data buffer associated with this BD is empty, or reception is currently in progress.

Offset + 0

RO1

Receive software ownership bit. Reserved for use by software. This read/write bit is not

modified by hardware, nor does its value affect hardware.

Offset + 0

Wrap. Written by user

0 The next buffer descriptor is found in the consecutive location.

1 The next buffer descriptor is found at the location defined in RBASE.

Offset + 0

Interrupt. Written by user

0 No interrupt is generated after this buffer is serviced.

1 IEVENT[RXB] or IEVENT[RXF] are set after this buffer is serviced. This bit can cause an

interrupt if enabled (IMASK[RXBEN] is set or IMASK[RXFEN] is set). If the user wants to

be interrupted only if RXF occurs, then the user must disable RXB (IMASK[RXBEN] is

cleared) and enable RXF (IMASK[RXFEN] is set).

Offset + 0

Last in frame. Written by TSEC

0 The buffer is not the last in a frame.

1 The buffer is the last in a frame.

Offset + 0

First in frame. Written by TSEC

0 The buffer is not the first in a frame.

1 The buffer is the first in a frame.

Offset + 0

—

Reserved

Offset + 0

Miss. Written by TSEC. (This bit is valid only if the L-bit is set and TSEC is in promiscuous

mode.) This bit is set by the TSEC for frames that were accepted in promiscuous mode, but

were flagged as a ‘miss’ by the internal address recognition; thus, while in promiscuous mode,

the user can use the M-bit to quickly determine whether the frame was destined to this station.

0 The frame was received because of an address recognition hit.

1 The frame was received because of promiscuous mode.

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