MPC8540 datasheet(759/1302 Pages) FREESCALE

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Initialization/Application Information

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

14-133

Initialize ECNTRL,

ECNTRL[0000_0000_0000_0000_0001_0000_0000_0000]

(This example has Statistics Enable = 1)

Initialize MAC Station Address,

MACSTNADDR2[0110_0000_0000_0010_0000_0000_0000_0000]

Set station address to 02_60_8C_87_65_43, for example.

(Note that PHY configuration register addresses are not necessarily consistent in all PHYs.)

Initialize MAC Station Address,

MACSTNADDR1[0100_0011_0110_0101_1000_0111_1000_1100]

Set station address to 02_60_8C_87_65_43, for example.

(Note that PHY configuration register addresses are not necessarily consistent in all PHYs.)

Assign a Physical address to the TBI so as to not conflict with the external PHY Physical address,

TBIPA[0000_0000_0000_0000_0000_0000_0000_0101]

Set to 05, for example.

(Note that PHY configuration register addresses are not necessarily consistent in all PHYs.)

Reset the management interface.

MIIMCFG[1000_0000_0000_0000_0000_0000_0000_0000]

Setup the MII Mgmt clock speed,

MIIMCFG[0000_0000_0000_0000_000_0000_0000_0101]

set source clock divide by 14, for example, to insure that EC_MDC clock speed is approximately 2.5 MHz.

Read MII Mgmt Indicator register and check for Busy = 0,

MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]

This indicates that the TSEC MII Mgmt bus is idle.

Set up the MII Mgmt for a write cycle to the external PHY Auxiliary Control and Status Register to configure the PHY

through the Management interface (overrides configuration signals of the PHY).

MIIMADD[0000_0000_0000_0000_0000_0000_0001_1100]

Perform an MII Mgmt write cycle to the external PHY

Writing to MII Mgmt Control with 16-bit data intended for the external PHY register,

MIIMCON[0000_0000_0000_0000_0000_0000_0000_0100]

Check to see if MII Mgmt write is complete

Read MII Mgmt Indicator register and check for Busy = 0,

MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]

This indicates that the write cycle was completed.

Set up the MII Mgmt for a write cycle to the external PHY Extended PHY control register 1 to set up the interface

mode selection.

MIIMADD[0000_0000_0000_0000_0000_0000_0001_0111]

Perform an MII Mgmt write cycle to the external PHY.

Write to MII Mgmt Control with 16-bit data intended for the external PHY register,

MIIMCON[0000_0000_0000_0000_0000_0000_0000_0000]

Check to see if MII Mgmt write is complete.

Read MII Mgmt Indicator register and check for Busy = 0,

MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]

This indicates that the write cycle was completed.

Set up the MII Mgmt for a write cycle to the external PHY Mode control register to set up the interface mode selection.

MIIMADD[0000_0000_0000_0000_0000_0000_0000_0000]

Table 14-124. MII Mode Register Initialization Steps (continued)

MPC8540 Datasheet(PDF) 759 Page - Freescale Semiconductor, Inc

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