MPC8540 datasheet(948/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

17-24

Freescale Semiconductor

RapidIO Interface

17.3.1.11 Processing Element Logic Layer Control Command and Status

The PELLCCSR, shown in Figure 17-13, is a read-only register. Additional details of this register

can be found in the Parallel RapidIO Interconnect Specification.

Table 17-17 describes the fields of the PELLCCSR.

17.3.1.12 Local Configuration Space Base Address 1 Command and Status

The local configuration space base address 1 command and status register (LCSBA1CSR), shown

in Figure 17-14, contains the 14 msbs of the double-word address, which represents the base

address for the device’s register space.

Port-write unit error

0 Received port-write packet contains no errors, for example, data is of legal size (64 bytes or less)

1 Received port-write packet contains fatal errors, for example, data is of illegal size (greater than 64

bytes). All incoming port-write transactions are discarded.

30–31

—

Reserved

28 29

R 0

EAC

Reset

0000_0000_0000_0000_0000_0000_0000_0001

Offset

0xC_004C

Figure 17-13. Processing Element Logic Layer Control Command and Status Register

(PELLCCSR)

Table 17-17. PELLCCSR Field Descriptions

Bits

Name

Description

0–28

—

Reserved

29–31

EAC

Extended addressing control. The RapidIO controller supports 34-bit addresses (read-only).

Table 17-16. PWDCSR Field Descriptions (continued)

Bits

Name

Description

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