MPC8540 datasheet(949/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

17-25

Table 17-18 describes the fields of the LCSBA1CSR.

17.3.1.13 Base Device ID Command and Status Register (BDIDCSR)

Figure 17-15 shows the BDIDSCR.

Table 17-19 describes the fields of the BDIDCSR.

14 15

LCSBA

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xC_005C

Figure 17-14. Local Configuration Space Base Address 1 Command and Status

Table 17-18. LCSBA1CSR Field Descriptions

Bits

Name

Description

0—

Reserved

1–14

LCSBA Local configuration space base address. These bits correspond to the 14 most-significant bits of the

34-bit RapidIO address space.

15–31

—

Reserved

15 16

R 0

BDID

Reset

0000_0000_(Value from configuration pins)_0000_0000_0000_0000

Offset

0xC_0060

Figure 17-15. Base Device ID Command and Status Register (BDIDCSR)

Table 17-19. BDIDCSR Field Descriptions

Bits

Name

Description

0–7

—

Reserved

8–15

BDID

Base device ID (RapidIO device ID). Value read from reset configuration pins.

For more information on the RapidIO device ID, see Section 4.4.3.11,

“RapidIO Device ID.”

16–31

—

Reserved

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