MPC8540 datasheet(953/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

17-29

17.3.1.19 Port General Control Command and Status Register (PGCCSR)

The PGCCSR, shown in Figure 17-21, reflects the state of the RapidIO port.

Table 17-25 describes the fields of the PGCCSR.

17.3.1.20 Port Link Maintenance Request Command and Status Register

(PLMREQCSR)

A write to the PLMREQCSR, shown in Figure 17-22, generates a link-request control symbol on

the RapidIO port interface. See the Parallel RapidIO Interconnect Specification for descriptions

of the reset command, input-status command and send-training commands.

123

H M D

Reset

(Value from configuration pins)_0000_0000_0000_0000_0000_0000_0000

Offset

0xC_013C

Figure 17-21. Port General Control Command and Status Register (PGCCSR)

Table 17-25. PGCCSR Field Descriptions

Bits

Name

Description

A host device is a device that is responsible for system exploration, initialization, and maintenance.

Agent (or slave) devices are initialized by host devices. Initialized from the host/agent configuration pin;

If host is sampled, H is set as host.

0 Agent device

1 Host device

Master enable bit. Controls whether or not a device is allowed to issue requests into the system. If the

master enable is not set, the device may only respond to requests. Initialized from the host/agent

configuration pin. Out of reset, if configured as a host (PGCCSR[H] is set), M and D are also set. If

configured as an agent (PGCCSR[H] is cleared), M and D are initialized by the host of the system.

0 Device is not enabled to issue requests into the system

1 Device is enabled to issue requests into the system

Discovery enable bit. This device has been located by the processing element responsible for system

configuration. Initialized from the host/agent configuration pin. Out of reset, if configured as a host

(PGCCSR[H] is set), bits M and D are also set. If configured as an agent (PGCCSR[H] is cleared), bits

M and D are initialized by the host of the system.

0 Device has not been discovered by system host

1 Device has been discovered by system host

3–31

—

Reserved

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