MPC8540 datasheet(951/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

17-27

Table 17-21 describes the field of the CTCSR.

17.3.1.16 8/16 LP-LVDS Port Maintenance Block Header 0 Command and

Status Register (PMBH0CSR)

The port maintenance block header 0 command and status register, shown in Figure 17-18,

contains the extended features pointer to the next extended features block and the extended

features ID that identifies this as the generic end point port maintenance block header.

Table 17-22 describes the fields of the PMBH0CSR.

17.3.1.17 Port Link Time-Out Control Command and Status Register

(PLTOCCSR)

The PLTOCCSR, shown in Figure 17-19, contains the time-out timer value used to monitor link

events, for example, between sending a packet and receiving the corresponding acknowledge.

Alternately, it can contain the value of the timer time-out between sending a link-request and

receiving the corresponding link-response. The reset value is the maximum time-out interval and

represents between three and five seconds.

Table 17-21. CTCSR Field Descriptions

Bits

Name

Description

0–31

Component tag. Identifying component tag for the RapidIO block.

015 16

EF_PTR

EF_ID

Reset

0000_0000_0000_0000_0000_0000_0000_0010

Offset

0xC_0100

Figure 17-18. 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status

Table 17-22. PMBH0CSR Field Descriptions

Bits

Name

Description

0–15

EF_PTR Extended features pointer. Points to the next extended features block. 0x0000 for the MPC8540.

16–31

EF_ID

Extended features ID. Identifies this as the generic end point port maintenance block header. 0x0002 for

the MPC8540.

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