MPC8540 datasheet(954/1302 Pages) FREESCALE

954 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

17-30

Freescale Semiconductor

RapidIO Interface

Table 17-26 describes the fields of the PLMREQCSR.

17.3.1.21 Port Link Maintenance Response Command and Status Register

(PLMRESPCSR)

A read from the PLMRESPCSR, shown in Figure 17-23, returns the status received in a

link-response control symbol.

Table 17-27 describes the fields of the PLMRESPCSR.

28 29

R 0

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xC_0140

Figure 17-22. Port Link Maintenance Request Command and Status Register

(PLMREQCSR)

Table 17-26. PLMREQCSR Field Descriptions

Bits

Name

Description

0–28

—

Reserved

29–31

Command. This is the command to be sent in the link-request control symbol.

See Table 17-85 for command symbol formats.

24 25

27 28

R RV 0

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xC_0144

Figure 17-23. Port Link Maintenance Response Command and Status Register

(PLMRESPCSR)

Table 17-27. PLMRESPCSR Field Descriptions

Bits

Name

Description

Response valid (clear on read)

0 If the link-request caused a link-response, the link-response has not yet been received. If the

link-request did not cause a link-response, the link-request has not yet been transmitted.

1 If the link-request caused a link-response, the link-response has been received and the status fields

are valid. If the link-request did not cause a link-response, the link-request has been transmitted.

1–24

—

Reserved

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