MPC8540 datasheet(957/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

17-33

17.3.1.24 Port Control Command and Status Register (PCCSR)

The PCCSR contains bits used for port control. Figure 17-26 shows the PCCSR.

Table 17-30 describes the fields of the PCCSR.

Input port error. (Bit reset, write-one-to-clear)

0 Input port operating properly

1 Input port encountered an unrecoverable error or output port failed error recover

Port initialization (read-only)

0 Input or output port not initialized

1 Input and output ports are initialized and can communicate with the adjacent device.

Port training mode (read-only)

Note: Set shortly after reset due to asynchronous interface crossing delay

0 Input and output ports initialized

1 Input and output ports are not initialized and are in training mode

R OPW

OPE OPD

0 IPW

IPE IPD

0 ECD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reset

0100_0100_0000_0000_0000_0000_0000_0000

Offset

0xC_015C

Figure 17-26. Port Control Command and Status Register (PCCSR)

Table 17-30. PCCSR Field Descriptions

Bits

Name

Description

OPW Operating width of the output port (read-only field)

0 Port operating in 8-bit mode

1Reserved

OPE

Output port transmit enable. Must equal the value of PCCSR[IPE] for the RapidIO controller to function

properly.

0 Port is stopped and not enabled to issue any packets except to respond to maintenance packets

1 Port is enabled to issue any packets

OPD

Output port drivers disable

0 Input receiver and/or output driver are enabled

1 Both the input receivers and output drivers are disabled.

3—

Reserved

IPW

Operating width of the input port (read-only field)

0 Port operating in 8-bit mode

1Reserved

Table 17-29. PESCSR Field Descriptions (continued)

Bits

Name

Description

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