MPC8540 datasheet(961/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

17-37

17.3.2.2.1 RapidIO Outbound Window Translation Address Registers 0–8

(ROWTARn)

The RapidIO outbound window translation address registers (ROWTARs) select the starting

addresses in the external address space for window hits within the outbound translation windows.

The new translated address is created by concatenating the transaction offset to this translation

address. The target ID is formed from the top eight bits of the translated address. This register takes

on one of two formats, determined by the RDTYP and WRTYP fields in the corresponding

attributes register (ROWARn), one for standard operations and one for maintenance operations.

See Section 17.7.1, “Outbound ATMU Translation,” for more information. Figure 17-30 shows

the ROWTARs as used in standard operations.

Figure 17-30. RapidIO Outbound Window Translation Address Registers 0–8 for Standard

Transactions (

ROWTARn)

Table 17-34 describes the fields of the ROWTARs for standard operations.

TRGTID

TREXAD

TRAD

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset 0xD_0C00, 0xD_0C20, 0xD_0C40, 0xD_0C60, 0xD_0C80, 0xD_0CA0, 0xD_0CC0, 0xD_0CE0, 0xD_0D00

Table 17-34. ROWTARn Standard Field Descriptions

Bits

Name

Description

0–1

—

Reserved

2–9

TRGTID Target ID for RapidIO packet

10–11

TREXAD Translation extended address of outbound window

The translation extended address correspond to bits 0–1 of the 34-bit RapidIO address.

12–31

TRAD

Translation address of outbound window

System address that represents the starting point of the outbound translated address. The

translation address must be aligned based on the size field. The translation address corresponds to

bits 2–21 of the 34-bit RapidIO address.

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