MPC8540 datasheet(960/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

17-36

Freescale Semiconductor

RapidIO Interface

injected once and the enable bit is cleared if error injection is enabled and SE is not set. The error

is injected continuously if both EN and SE are set. It stops if software clears the enable bit. After

setting the enable bit, software can monitor the injection of the error by polling the register and

observing the enable bit being cleared.

Figure 17-29. Port Error Injection Register (PEIR)

Table 17-33 describes the fields of the PEIR.

17.3.2.2 ATMU Registers

Although the Parallel RapidIO Interconnect Specification allows for 48- and 64-bit addresses, the

MPC8540 implementation only allows for 34-bit RapidIO addresses. ATMU window misses use

the window 0 register set by default. Overlapping window hits result in the use of the lowest

number window register set hit. For both inbound and outbound translation, the smallest window

size is 4 Kbytes and the largest window size is 4 Gbytes. See Section 17.7, “ATMU (Address

Translation and Mapping Unit),” for more information.

1516

232425 26 27

0 0

EM SE SS EN

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xD_0014

Table 17-33. PEIR Field Descriptions

Bits

Name

Description

0–7

Byte mask. Indicates on which bit of the byte to inject error

8–15

—

Reserved

16–23

Word count. Number of words to count before injecting error

24–25

Byte count. Byte within the specified word count on which to inject error

26–27

—

Reserved

Error mirror. Setting EM when BC is 00 causes the error to be mirrored to 10 and when BC is 01, the

error is mirrored to 11. This gives better flexibility for error injection. For example, an EOP symbol can

be converted to a STOMP symbol using this bit. Setting EM when BC is 10 or 11 causes an illegal

condition.

Software enable. If SE and EN are set, an error continues to be injected until EN is cleared by software.

Symbol select. Packet or control symbol selection

0 Inject error in a packet.

1 Inject error in a control symbol.

Enabled to start counting and inject error at the specified word count, byte within the word, and bit

within the byte. Hardware injects error and clears this bit.

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