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MPC8540 Datasheet(PDF) 962 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 962 Page - Freescale Semiconductor, Inc

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
17-38
Freescale Semiconductor
RapidIO Interface
Figure 17-31 shows the ROWTARs for maintenance transactions.
Figure 17-31. RapidIO Outbound Window Translation Address Registers 0–8 for
Maintenance Transactions (
ROWTARn)
Table 17-35 describes ROWTARs fields for maintenance transactions. For maintenance
transactions, the hop count is formed from ROWTAR[12–19]. Similarly, the upper 12 bits of the
maintenance offset is formed from ROWTAR[20–31]. The rest of the maintenance offset is
formed from the untranslated address.
17.3.2.2.2 RapidIO Outbound Window Base Address Registers 1–8
(ROWBARn)
The RapidIO outbound window translation address registers (ROWBARn), shown in
Figure 17-32, select the base address for the windows that are translated to an alternate system
address space. Addresses for outbound transactions are compared to these windows. If such a
transaction does not fall within one of these spaces the transaction is forwarded through the
window 0 register set. Since window 0 is the default window, and default translation does not
require a base address register, ROWBAR0 is not implemented.
Figure 17-32. RapidIO Outbound Window Base Address Registers 1–8
(ROWBARn)
0
1
2
9
10 11 12
19 20
31
R0
0
TRGTID
00
HOP_COUNT
CFG_OFFSET
W
Reset
0000_0000_0000_0000_0000_0000_0000_0000
Offset
0xD_0C00, 0xD_0C20, 0xD_0C40, 0xD_0C60, 0xD_0C80, 0xD_0CA0, 0xD_0CC0, 0xD_0CE0, 0xD_0D00
Table 17-35. ROWTARn Maintenance Field Descriptions
Bits
Name
Description
0–1
—
Reserved
2–9
TRGTID
Target ID for RapidIO Packet
10–11
—
Reserved
12–19
HOP_COUNT Hop count of maintenance transaction
20–31
CFG_OFFSET Upper 12 bits of maintenance offset. The lower 9 bits of the 21-bit RapidIO maintenance
offset are formed from the untranslated address.
011 12
31
R 00000
00
0
0
0
0
0
BADD
W
Reset
0000_0000_0000_0000_0000_0000_0000_0000
Offset
0xD_0C028, 0xD_0C48, 0xD_0C68, 0xD_0C88, 0xD_0CA8, 0xD_0CC8, 0xD_0CEB, 0xD_0D08



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