MPC8540 datasheet(966/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

17-42

Freescale Semiconductor

RapidIO Interface

Table 17-39 describes the fields of the RIWBARs.

17.3.2.2.6 RapidIO Inbound Window Attributes Registers 0–4 (RIWARn)

The RapidIO inbound window attributes registers (RIWARs) define the window size to translate

and other attributes for the translation. The largest window size allowed is 4 Gbytes. Figure 17-38

and Figure 17-37 show the RIWARs.

Figure 17-37. RapidIO Inbound Window Attributes Register 0 (RIWAR0)

Figure 17-38. RapidIO Inbound Window Attributes Registers 1–4

(RIWARn)

Table 17-40 describes the fields of the RIWARs.

Table 17-39.

RIWBARn Field Descriptions

Bits

Name

Description

0–9

—

Reserved

10–11

BEXAD Base extended address of inbound window. Field represents bits 0–1 of a 34-bit address.

12–31

BADD

Base address of inbound window. Source address that is the starting point for the inbound translation

window. The window must be aligned based on the size selected in the window size bits. This

corresponds to bits 2–21 of a 34-bit address.

11 12

15 16

19 20

25 26

R EN 0

00000

TGINT

RDTYP

WRTYP

000000

SIZE

Reset

1000_0000_0000_0100_0100_0000_0001_1111

Offset

0xD_0DF0

11 12

15 16

19 20

25 26

TGINT

RDTYP

WRTYP

000000

SIZE

Reset

0000_0000_0000_0100_0100_0000_0001_1111

Offset

0xD_0DD0, 0xD_0DB0, 0xD_0D90, 0xD_0D70

Table 17-40. RIWARn Field Descriptions

Bits

Name

Description

Window address translation enable. Note that for RIWAR0 the enable bit is read only and hardwired to 1.

0 Address translation disabled

1 Address translation enabled

1–7

—

Reserved

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