MPC8540 datasheet(967/1302 Pages) FREESCALE

967 / 1302 page

Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

17-43

17.3.2.3 Error Management Registers

RapidIO error management registers allow configuration of RapidIO error detection, capture, and

reporting. Bits in the port notification/fatal error detect register (PNFEDR) report which port

notification or error was detected, subject to individual detection enable bit settings in the port

notification/fatal error detect disable register (PNFEDiR). Upon detecting a port notification or

8–11

TGINT

Target interface

0000 PCI/PCI-X

0001–1110 Reserved

1111 Local memory (DDR SDRAM, local bus controller (LBC), L2 cache/SRAM)

Note: If TGINT is set to an I/O port (for example, PCI/PCI-X) rather than local memory space, attributes

for the external I/O transaction are assigned in an outbound ATMU of that I/O controller.

12–15 RDTYP Read transaction type. Transaction type to run if access is a read. The field description depends on the

target of the transaction (to I/O interface or to local memory).

Following are the transaction type settings for reads from the PCI/PCI-X interface:

0000–0011 Reserved

0100 Read

0101–1111 Reserved

The following are the transaction type settings for reads from local memory:

0000–0011 Reserved

0100 Received read; do not snoop processor core (e500)

0101 Received read; snoop processor core (e500)

0110 Reserved

0111 Received read; unlock L2 cache line

1000–1111 Reserved

16–19 WRTYP Write transaction type. Transaction type to run if access is a write. The field description depends on the

target of the transaction (to I/O interface or to local memory).

Following are the transaction type settings for writes to the PCI/PCI-X interface:

0000–0011 Reserved

0100 Write

0101–1111 Reserved

Following are the transaction type settings for writes to local memory:

0000–0011 Reserved

0100 Received write; don’t snoop processor core (e500)

0101 Received write; snoop processor core (e500)

0110 Received write; allocate L2 cache line

0111 Received write; allocate and lock L2 cache line

1000–1111 Reserved

20–25

—

Reserved

26–31

SIZE

Inbound window size. Inbound window size N which is the encoded 2n+1 bytes window size. The

smallest window size is 4 Kbytes. The largest window size is 4 Gbytes.

00_0000–00_1010 Reserved

00_1011 4 Kbytes

00_1100 8 Kbytes

...

01_1111 4 Gbytes

10_0000–11_1111 Reserved

Table 17-40. RIWARn Field Descriptions (continued)

Bits

Name

Description

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