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MPC8540 Datasheet(PDF) 971 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 971 Page - Freescale Semiconductor, Inc

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Memory Map/Register Definition
MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
Freescale Semiconductor
17-47
17.3.2.3.2 Port Notification/Fatal Error Detect Disable Register
(PNFEDiR)
The PNFEDiR individually disables the detection of each port notification or fatal error defined
in the PNFEDR. Figure 17-40 shows the PNFEDiR.
Figure 17-40. Port Notification/Fatal Error Detect Disable Register (PNFEDiR)
Table 17-42 describes the fields of the PNFEDiR.
01
2
3
5
6
7
8
9
10
11
12
13
14
15
R
0
IAXD OAXD
0
0
0
ITD
MSD NTID
SD
DSD
BMD
ETD
RTD
RERD
LTD
W
Reset
0000_0000_0000_0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
RSTD NAD IRFD URDD URD URSD IWRD IRSFD IRTD BRRD BWRD URSSD URESD URSDD MERD MDFD
W
Reset
0000_0000_0000_0000
Offset
0xD_0E04
Table 17-42. PNFEDiR Field Descriptions
Bits
Name
Description
0—
Reserved
1
IAXD
Inbound ATMU window crossing error detection disable
0 Error detection enabled
1 Error detection disabled
2
OAXD
Outbound ATMU window crossing error detection disable
0 Error detection enabled
1 Error detection disabled
3–5
—
Reserved
6
ITD
Illegal transaction target error detection disable
0 Error detection enabled
1 Error detection disabled
7
MSD
Message size error detection disable
0 Error detection enabled
1 Error detection disabled
8
NTID
Missing idle after training error detection disable
0 Error detection enabled
1 Error detection disabled
9
SD
Message segment error detection disable
0 Error detection enabled
1 Error disabled



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