MPC8540 datasheet(968/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

17-44

Freescale Semiconductor

RapidIO Interface

error, an interrupt is generated subject to the interrupt enable bit settings in the port

notification/fatal error interrupt enable register (PNFEIER); the port error capture status register

(PECSR) indicates whether a valid packet was captured when the port notification or fatal error

occurred. If a packet is captured (PECSR[V] is set), packet information may be found in the error

packet capture registers (EPCRn). The packet format type, as captured in EPCR0[PFT],

determines the format of the remaining packet data captured in EPCR1 and EPCR2.

Bits in the port recoverable error detect register (PREDR) report which recoverable errors have

been detected.

The port error recovery threshold register (PERTR) and the port retry threshold register (PRTR)

allow software to assign and monitor the recovery and retry thresholds, which are referenced by

hardware before reporting a recovery error (PNFEDR[ETE]) or a retry error (PNFEDR[RTE]).

17.3.2.3.1 Port Notification/Fatal Error Detect Register (PNFEDR)

The PNFEDR, shown in Figure 17-39, reflects individual port notifications and fatal errors that

the RapidIO controller has detected. Each bit is cleared when a 1 is written to it.

Figure 17-39. Port Notification/Fatal Error Detect Register (PNFEDR)

Table 17-41 describes the fields of the PNFEDR.

111213

MFE IAXE OAXE

ITE

MSE NTIE

DSE

MLE

ETE

RTE

RERE

LTE

Reset

0000_0000_0000_0000

RSTE NAE IRFE URDE URE URSE IWRE IRSFE IRTE BRRE BWRE URSSE URESE URSDE MERE MDFE

Reset

0000_0000_0000_0000

Offset

0xD_0E00

Table 17-41. PNFEDR Field Descriptions

Bits

Name

Description

MFE

Multiple fatal errors. (Bit reset, write-one-to-clear)

0 Multiple fatal RapidIO errors of the same type were not detected.

1 Multiple fatal RapidIO errors of the same type were detected.

IAXE

Inbound ATMU window crossing error. (Bit reset, write-one-to-clear)

0 No inbound window crossing error

1 This error indicates that an inbound transaction either crosses the boundary of its ATMU window or

crosses into a higher priority ATMU window.

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