MPC8540 datasheet(965/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

17-41

Figure 17-35. RapidIO Inbound Window Translation Address Registers 0–4

(RIWTARn)

Table 17-38 describes the fields of the RIWTARs.

17.3.2.2.5 RapidIO Inbound Window Base Address Registers 1–4

(RIWBARn)

RapidIO inbound window translation address registers (RIWBARs), shown in Figure 17-36,

select the base address for windows that are translated to an alternate system address space.

Addresses for inbound transactions are compared to these windows. If such a transaction does not

fall in the LCSBA1CSR window or one of these spaces, the transaction is forwarded through the

window 0 register set. Since window 0 is the default and default translation does not require a base

address register, RIWBAR0 is not implemented.

Figure 17-36. RapidIO Inbound Window Base Address Registers 1–4

(RIWBARn)

011 12

R 0

0000

TRAD

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xD_0DE0, 0xD_0DC0, 0xD_0DA0, 0xD_0D80, 0xD_0D60

Table 17-38. RIWTARn Field Descriptions

Bits

Name

Description

0–11

—

Reserved

12–31

TRAD Translation address of inbound window. System address that represents the starting point of the

inbound translated address. The translation address must be aligned based on the size field. This

corresponds to bits 0–19 of the 32-bit address.

R 0

000

BEXAD

BADD

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xD_0DC8, 0xD_0DA8, 0xD_0D88, 0xD_0D68

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