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MPC8540 Datasheet(PDF) 973 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 973 Page - Freescale Semiconductor, Inc

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Memory Map/Register Definition
MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
Freescale Semiconductor
17-49
17.3.2.3.3 Port Notification/Fatal Error Interrupt Enable Register
(PNFEIER)
The PNFEIER, shown in Figure 17-41, individually enables each detected port notification or fatal
error to generate an interrupt to the programmable interrupt controller (PIC).
Figure 17-41. Port Notification/Fatal Error Interrupt Enable Register (PNFEIER)
25
BRRD
Bad read response error detection disable
0 Error detection enabled
1 Error detection disabled
26
BWRD
Bad write response error detection disable
0 Error detection enabled
1 Error detection disabled
27
URSSD
Unexpected response data size error detection disable
0 Error detection enabled
1 Error detection disabled
28
URESD
Unsolicited response without data error detection disable
0 Error detection enabled
1 Error detection disabled
29
URSDD
Unsolicited response with data error detection disable
0 Error detection enabled
1 Error detection disabled
30
MERD
Message error response error detection disable
0 Error detection enabled
1 Error detection disabled
31
MDFD
Message descriptor fetch error detection disable
0 Error detection enabled
1 Error detection disabled
0
1
2
3
5
6
78
9
1011
12
13
14
15
R
0
IAXIE OAXIE
0
0
0
ITIE
MSIE NTIIE
SIE
DSIE
BMIE
ETIE
RTIE
RERIE LTIE
W
Reset
0000_0000_0000_0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
RSTIE NAIE IRFIE URDIE URIE URSIE IWRIE IRSFIE IRTIE BRRIE BWRIE URSSIE URESIE URSDIE MERIE MDFIE
W
Reset
0000_0000_0000_0000
Offset
0xD_0E08
Table 17-42. PNFEDiR Field Descriptions (continued)
Bits
Name
Description



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