MPC8540 datasheet(976/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

17-52

Freescale Semiconductor

RapidIO Interface

17.3.2.3.4 Port Error Capture Status Register (PECSR)

The PECSR, shown in Figure 17-42, indicates whether a valid packet has been captured when a

port notification or fatal error has occurred. Hardware sets PECSR[V] and software is expected to

clear it after processing the error to capture future error packets.

Figure 17-42. Port Error Capture Status Register (PECSR)

Table 17-44 describes the fields of the PECSR.

17.3.2.3.5 Error Packet Capture Register 0 (EPCR0)

The EPCR0, shown in Figure 17-43, captures the first 32 bits of an inbound packet that caused a

port notification or fatal error. The format of the first 32 bits of an inbound packet are the same for

all packet format types.

Figure 17-43. Error Packet Capture Register 0 (EPCR0)

30 31

R 0

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xD_0E0C

Table 17-44. PECSR Field Descriptions

Bits

Name

Description

0–30

—

Reserved

Packet register information valid

0 Packet capture registers do not contain valid information.

1 Packet capture registers contain valid information.

10 1112

1516

23 24

R ¬S R R

PFT

DID

SID

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xD_0E10

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