MPC8540 datasheet(977/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

17-53

Table 17-45 describes the fields of the EPCR0.

17.3.2.3.6 Error Packet Capture Register 1 (EPCR1)

EPCR1 captures a portion of an inbound packet that caused a port notification or a fatal error. The

format of the EPCR1 contents vary subject to the packet format type as captured in EPCR0[PFT].

The various content formats of EPCR1 are described in Section 17.3.2.3.7, “EPCR1—Type 1

Packet Format,” through Section 17.3.2.3.15, “EPCR1—Type 13 Packet Format.”

17.3.2.3.7 EPCR1—Type 1 Packet Format

Figure 17-44 describes EPCR1 for a type 1 packet format (EPCR0[PFT] = 1).

Figure 17-44. Error Packet Capture Register 1 (EPCR1)—Type 1 Packet Format

Table 17-45. EPCR0 Field Descriptions

Bits

Name

Description

S-bit of the packet

1–3

AckID field of a packet

These bits correspond to bits 4–7 of a packet header. In the packet definition bit 4 is a reserved packet

field, bit 5 is S-complement, and bits 6 and 7 are reserved packet fields. (Bits 4, 6 and 7 are reserved

packet fields, not reserved register fields.)

¬S

6–7

8–9

Priority field of a packet

10–11

Transport type field of a packet

12–15

PFT

Packet format type field of a packet

16–23

DID

Destination ID field of a packet

24–31

SID

Source ID field of a packet

15 16

23 24

TRANS

RDSZ

STID

SECID

SECTID

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xD_0E14

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