MPC8540 datasheet(979/1302 Pages) FREESCALE

979 / 1302 page

Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

17-55

Table 17-48 describes the EPCR1 fields for a type 5 packet format (EPCR0[PFT] = 5).

17.3.2.3.10EPCR1—Type 6 Packet Format

Figure 17-47 shows the EPCR1 for a type 6 packet format (EPCR0[PFT] = 6).

Figure 17-47. Error Packet Capture Register 1 (EPCR1)—Type 6 Packet Format

Table 17-49 describes the field of the EPCR1 for a type 6 packet format (EPCR0[PFT] = 6).

17.3.2.3.11 EPCR1—Type 8 Request Packet Format

Figure 17-48 shows EPCR1 for a type 8 request packet format (EPCR0[PFT] = 8 and

EPCR1[TRANS] = 0 or 1).

Figure 17-48. Error Packet Capture Register 1 (EPCR1)—Type 8 Request Packet Format

Table 17-48. EPCR1

Type 5 Field Descriptions

Bits

Name

Description

0–3

TRANS Transaction field of a packet

4–7

WRSZ

Write size

8–15

STID

Source transaction ID

16–31

—

Reserved

R 0

000000000000

0000

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xD_0E14

Table 17-49. EPCR1

Type 6 Field Descriptions

Bits

Name

Description

0–31

—

Reserved

15 16

TRANS

RDSZ/WRSZ

STID

0000

000000

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xD_0E14

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