MPC8540 datasheet(983/1302 Pages) FREESCALE

983 / 1302 page

Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

17-59

Table 17-55 shows EPCR2 for a type 1, 2, or 5 packet format (EPCR0[PFT] = 1, 2, or 5).

17.3.2.3.18EPCR2—Type 6 Packet Format

Figure 17-54 describes the EPCR2 for a type 6 packet format (EPCR0[PFT] = 6).

Figure 17-54. Error Packet Capture Register 2 (EPCR2)—Type 6 Packet Format

Table 17-56 describes the EPCR2 fields for a type 6 packet format (EPCR0[PFT] = 6).

17.3.2.3.19EPCR2—Type 8 Request Packet Format

Figure 17-55 shows EPCR2 for a type 8 request packet format (EPCR0[PFT] = 8 and

EPCR1[TRANS] = 0 or 1).

Figure 17-55. Error Packet Capture Register 2 (EPCR2)—Type 8 Request Packet Format

Table 17-55. EPCR2 Type 1, 2, or 5 Field Descriptions

Bits

Name

Description

0–28

PAD

Address[2:30] field of a packet

WDPTR

Word pointer field of a packet, which is used in conjunction with the data size field

30–31

XAMSBS Address[0:1] field of a packet

28 29

PAD

0 XAMSBS

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xD_0E18

Table 17-56. EPCR2 Type 6 Field Descriptions

Bits

Name

Description

0–28

PAD

Address[2:30] field of a packet

—

Reserved

30–31

XAMSBS Address[0:1] field of a packet

HPCNT

MNTOF

WDPTR XAMSBS

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xD_0E18

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