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MPC8540 Datasheet(PDF) 984 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 984 Page - Freescale Semiconductor, Inc |
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984 / 1302 page ![]() MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 17-60 Freescale Semiconductor RapidIO Interface Table 17-57 describes the fields of the EPCR2 for a type 8 request packet format (EPCR0[PFT] = 8 and EPCR1[TRANS] = 0 or 1). 17.3.2.3.20EPCR2—Type 8 Response Packet Format Figure 17-56 shows EPCR2 for a type 8 response packet format (EPCR0[PFT] = 8 and EPCR1[TRANS] = 2 or 3). Figure 17-56. Error Packet Capture Register 2 (EPCR2)—Type 8 Response Packet Format Table 17-58 describes EPCR2 for a type 8 response packet format (EPCR0[PFT] = 8 and EPCR1[TRANS] = 2 or 3). 17.3.2.3.21EPCR2—Type 10 Packet Format Figure 17-57 describes the EPCR2 for a type 10 packet format (EPCR0[PFT] = 10). Figure 17-57. Error Packet Capture Register 2 (EPCR2)—Type 10 Packet Format Table 17-57. EPCR2 Type 8 Request Field Descriptions Bits Name Description 0–7 HPCNT Hop count field of a packet 8–28 MNTOF Maintenance offset field of a packet 29 WDPTR WdPtr field of a packet 30–31 XAMSBS Address[0:1] field of a packet 07 8 31 R HPCNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000 00 000 0 W Reset 0000_0000_0000_0000_0000_0000_0000_0000 Offset 0xD_0E18 Table 17-58. EPCR2 Type 8 Response Field Descriptions Bits Name Description 0–7 HPCNT Hop count field of a packet 8–31 — Reserved 015 16 31 R INFO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0000_0000_0000_0000_0000_0000_0000_0000 Offset 0xD_0E18 |
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