MPC8540 datasheet(988/1302 Pages) FREESCALE

988 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

17-64

Freescale Semiconductor

RapidIO Interface

17.3.2.3.24Port Error Recovery Threshold Register (PERTR)

Figure 17-60 shows the PERTR.

Figure 17-60. Port Error Recovery Threshold Register (PERTR)

Table 17-62 describes the fields of the PERTR.

17.3.2.3.25Port Retry Threshold Register (PRTR)

Figure 17-61 shows the PRTR.

Figure 17-61. Port Retry Threshold Register (PRTR)

1516

2324

R 0 0 0 0 0

0 0 0

RCTT

RCC

Reset

0000_0000_1111_1111_0000_0000_0000_0000

Offset

0xD_0E28

Table 17-62. PERTR Field Descriptions

Bits

Name

Description

0–7

—

Reserved

8–15

RCTT Recovery threshold trigger. These bits provide the threshold value for the number of successful

transmission error recoveries before reporting an error condition.

16–23

—

Reserved

24–31

RCC

Recovery counter. Maintains a count of the number of times the port has successfully recovered from

a transmission error. An error is reported (PNFEDR[ETE] is set) if this value equals the value

contained in the recovery threshold trigger field and if reporting is enabled (PNFEDiR[ETD] is cleared).

15 1623 2431

R 0 0 0

0 0 0 0

RTT

Reset

0000_0000_1111_1111_0000_0000_0000_0000

Offset

0xD_0E2C

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