MPC8540 datasheet(989/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

17-65

Table 17-63 describes the fields of the PRTR.

17.3.3 RapidIO Message Unit Registers

This section describes RapidIO outbound and inbound message registers, doorbell registers and

port-write registers. Refer to Section 17.8, “RapidIO Message Unit,” for additional information

about how these registers affect the message unit.

17.3.3.1 RapidIO Outbound Message Registers

The registers in this section control RapidIO outbound messages. The following sections provide

descriptions of these registers. Additional information may be found in the Parallel RapidIO

Interconnect Specification.

17.3.3.1.1 Outbound Mode Register (OMR)

The outbound mode register (OMR) allows software to start a message operation and to control

various message operation characteristics. Figure 17-62 shows the OMR.

Figure 17-62. Outbound Mode Register (OMR)

Table 17-63. PRTR Field Descriptions

Bits

Name

Description

0–7

—

Reserved

8–15

RTT

Retry threshold trigger. These bits provide the threshold value for the number of consecutive ack

retries received for an outbound packet before reporting an error condition.

16–23

—

Reserved

24–31

Retry counter. Maintains a count of the number of consecutive times the port has received an ack retry

for an outbound packet. An error is reported (PNFEDR[RTE] is set) if this value equals the value

contained in the retry threshold trigger field and if reporting is enabled (PNFEDiR[RTD] is cleared).

101112

15 16

19 20 21

26 27 28

R 0 000000000 0

DES_SEN

00 00

CIRQ_SIZ

QOIE QFIE

QEIE EIE

MUTM MUI MUS

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xD_1000

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