MPC8540 datasheet(985/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

17-61

Table 17-59 describes EPCR2 for a type 10 packet format (EPCR0[PFT] = 10).

17.3.2.3.22EPCR2—Type 11 or 13 Packet Format

Figure 17-58 shows EPCR2 for a type 11 or 13 packet format (EPCR0[PFT] = 11 or 13).

Figure 17-58. Error Packet Capture Register 2 (EPCR2)—Type 11 or 13 Packet Format

Table 17-60 describes EPCR2 for a type 11 or 13 packet format (EPCR0[PFT] = 11 or 13).

17.3.2.3.23Port Recoverable Error Detect Register (PREDR)

The PREDR, described in Figure 17-59, indicates the recoverable errors detected on RapidIO.

Figure 17-59. Port Recoverable Error Detect Register (PREDR)

Table 17-59. EPCR2 Type 10 Field Descriptions

Bits

Name

Description

0–15

INFO Information field of a packet

16–31

—

Reserved

R 0

000000000000

00000

000000

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xD_0E18

Table 17-60. EPCR2 Type 11 or 13 Field Description

Bits

Name

Description

0–31

—

Reserved

MRE

ETE

ISE ICCE IAOSE IUAE IBCE IE256E INAIE INAUA

Reset

0000_0000_0000_0000

INACC INAPS INABC INASE INAGE URE UAE ABRE UTE USE

ULE

UEE LRE

FAE

FTEE

ATE

Reset

0000_0000_0000_0000

Offset

0xD_0E20

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