MPC8540 datasheet(982/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

17-58

Freescale Semiconductor

RapidIO Interface

17.3.2.3.15EPCR1—Type 13 Packet Format

Figure 17-52 describes the EPCR1 for a type 13 packet format (EPCR0[PFT] = 13).

Figure 17-52. Error Packet Capture Register 1 (EPCR1)—Type 13 Packet Format

Table 17-54 describes EPCR1 fields for a type 13 packet format (EPCR0[PFT] = 13).

17.3.2.3.16Error Packet Capture Register 2 (EPCR2)

This register captures another portion of an inbound packet that caused a port notification or a fatal

error. The format of the contents of this register are vary subject to the packet format type as

captured in EPCR0[PFT]. The various content formats of this register are described in

Section 17.3.2.3.17, “EPCR2—Type 1, 2, or 5 Packet Format,” through Section 17.3.2.3.22,

“EPCR2—Type 11 or 13 Packet Format.”

17.3.2.3.17EPCR2—Type 1, 2, or 5 Packet Format

Figure 17-53 shows EPCR2 for a type 1, 2, or 5 packet format (EPCR0[PFT] = 1, 2, or 5).

Figure 17-53. Error Packet Capture Register 2 (EPCR2)—Type 1, 2, or 5 Packet Format

15 16

TRANS

STAT

STID

000

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xD_0E14

Table 17-54. EPCR1 Type 13 Field Descriptions

Bits

Name

Description

0–3

TRANS Transaction field of a packet

4–7

STAT

Status field of a packet

8–15

STID

Source transaction ID

16–31

—

Reserved

PAD

WDPTR XAMSBS

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xD_0E18

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