MPC8540 datasheet(991/1302 Pages) FREESCALE

991 / 1302 page

Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

17-67

17.3.3.1.2 Outbound Status Register (OSR)

The outbound status register (OSR), shown in Figure 17-63, reports various message unit

conditions during and after a message operation. Writing a 1 to a writable condition bit in OSR

clears it.

Figure 17-63. Outbound Status Register (OSR)

Table 17-65 describes the fields of the OSR.

MUI

Message unit increment. Software sets MUI after writing a descriptor to memory. Hardware then

increments the ODQEPAR and clears this bit.Always reads as 0 if MUS is set

MUS

Message unit start

• Direct mode: a 0 to 1 transition while the message unit is not busy (OSR[MUB] = 0) starts the

message unit. A 1 to 0 transition has no effect.

• Chaining mode: a 0 to 1 transition while the message unit is not busy (OSR[MUB] = 0)

initializes the message unit in chaining mode and causes the outbound descriptor queue

dequeue pointer address to be stored as the base address of the circular descriptor queue. If

MUS is set, the message unit starts each time the enqueue and dequeue pointers are not

equal and an overflow of the circular descriptor queue has not been detected. A 1 to 0

transition while the message unit is busy halts the message unit after the current descriptor is

processed. The message unit must be re-initialized after this halt condition.

010

11 12

24 25

R0 00000000 0 0 QF 0 0 0 0 0 000000 0

QOI QFI

0MUB

EOMI QEI

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xD_1004

Table 17-65. OSR Field Descriptions

Bits

Name

Description

0–10

—

Reserved

Queue full (read-only)

0 Queue not full

1 The queue has become full.

12–23

—

Reserved

Transaction error

0 No transaction error

1 There was an error condition during the message operation. The message unit has received a

response error and halts. An interrupt is generated if OMR[IEI] is set (Bit reset, write-one-to-clear,

resuming message unit operation)

—

Reserved

Table 17-64. OMR Field Descriptions (continued)

Bits

Name

Description

MPC8540 Datasheet(PDF) 991 Page - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 991 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL